The present invention relates to a semiconductor device especially including SRAM cells.
FPGA (Field Programmable Gate Array) is an LSI which can be programmed freely by users in fields.
FPGA comprises a logic block (variable logic block) for performing a desired logical function, based on data set in the memory cells, and an interconnection region (variable interconnection region) for setting a desired interconnection path, based on the data set in the memory cells.
The memory cells provided in the logic blocks and the interconnection regions are, e.g., SRAM cells.
The SRAM cells provided in the proposed FPGA will be explained with reference to FIG. 20. FIG. 20 is a plan view of an SRAM cell of the proposed semiconductor device.
As illustrated in FIG. 20, a p-type well 122 and an n-type well 124 are formed on a semiconductor substrate. A device isolation region 128 for defining the device regions 126a, 126b is formed on the semiconductor substrate with the p-type well 122 and the n-type well 124 formed on. Gate interconnections 132a–132c are formed on the semiconductor substrate with a gate insulation film (not illustrated) formed therebetween.
The gate interconnection 132a is formed in a T-shape and crosses the device region 126a. The gate interconnection 132a includes the gate electrode of a load transistor L1 and the gate electrode of a driver transistor D1 and commonly connects the gate electrode of the load transistor L1 and the gate electrode of the driver transistor D1. In the device region 126a on both side of the gate electrode 132a, a p-type source diffused layer 134, 135 is formed. The gate electrode 132a and the source/drain diffused layer 134, 135 constitute the load transistor L1. In the device region 126a on both sides of the gate electrode 132a, an n-type source/drain diffused layer 136, 137 is formed. The gate electrode 126a and the source/drain diffused layer 136, 137 constitute the driver transistor D1.
The gate interconnection 132b is formed in a T-shape and crosses the device region 126b. The gate interconnection 132b includes the gate electrode of a load transistor L2 and the gate electrode of the driver transistor D2 and commonly connects the gate electrode of load transistor L2 and the gate electrode of the driver transistor D2. In the device region 126b on both sides for the gate electrode 132b, the p-type source/drain diffused layer 138, 139 is formed. The gate electrode 132b and the source/drain diffused layer 138, 139 constitute a load transistor L2. In the device region 126b on both sides of the gate electrode 132b, then-type source/drain diffused layer 140, 141 is formed. The gate electrode 132b and the source/drain diffused layer 140, 141 constitute a driver transistor D2.
The gate interconnection 132c is formed linearly and crosses the device regions 126a, 126b. The gate interconnection 132c includes the gate electrode of a transfer transistor T1 and the gate electrode of a transfer transistor T2 and commonly connects the gate electrode of the transfer transistor T1 and the gate electrode of the transfer transistor T2. In the device region 126a on both sides of the gate electrode 132c, the source/drain diffused layer 137, 142 is formed. The gate electrode 132c and the source/drain diffused layer 137, 142 constitute a transfer transistor T1. In the device region 126b on both sides of the gate electrode 132c, the source/drain diffused layer 140, 143 is formed. The gate electrode 132c and the source/drain diffused layer 140, 143 constitute the transfer transistor T2.
These transistors L1, L2, D1, D2, T1, T2 are connected to a source voltage, earth voltage, bit lines, etc. via a conductor plug 150, etc.
The SRAM cell of the proposed semiconductor substrate is thus constituted.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 9-148440
[Patent Reference 2]
Specification of U.S. Pat. No. 6,400,592